The present invention relates to a digital adaptive channel equalizer suitable for use with a high-speed serial interface (HSSI).
Communication through a band-limited channel is affected by inter-symbol interference (ISI), which is dependent on signal frequency and channel characteristics. When a signal is distorted by ISI, an eye pattern (eye opening) closes at an input of a receiver. As a result, the recovery of transmission data becomes difficult, and the Bit Error Rate (BER) increases. Also, the degree of distortion (amplitude or phase distortion) caused by the communication channel varies based on factors such as the bandwidth, length, and attenuation of the channel. The effect of the distortion is more pronounced in a communication channel that operates at frequency bands exceeding 1 GHz, particularly, multi-Gbps bands. For such high speed serial communication on a band limited channel, a channel equalizer is used to equalize waveforms by compensating for waveform distortion, which includes ISI.
Channel equalizers are broadly classified as analog equalizers and digital equalizers. “Convergence Analysis of the Cascade Second Order Adaptive Line Equalizer” by Kwisung Yoo, Gunhee Han and Hongil Yoon, IEEE Transactions on Circuits and Systems II, Vol. 53, No. 6, June 2006 describes an example of an analog equalizer. A typical analog equalizer includes analog components such as an equalization filter and an amplifier. In addition, the analog equalizer uses complex analog circuits adapted to handle a high serial bit rate frequency (e.g., GHz). An analog custom circuit is used to equalize the received data prior to converting the received data to digital data.
FIG. 1 shows one example of a conventional receiver system 10 including an analog equalizer (analog adaptive channel equalizer). The analog equalizer includes an equalization filter 12, a slicer 14, and an equalization control circuit 16. The equalization filter 12 includes a variable gain amplifier (hereinafter VGA) 18 and receives serial data transmitted through a communication channel (not shown) as received signal r(t). Further, the equalization filter 12 receives a gain control signal 20 from the equalization control circuit 16 and adjusts the gain of the VGA 18 based on the gain control signal 20 to set an equalization amount (i.e., distortion cancellation amount) of the received signal r(t). The slicer 14 receives an input signal q1(t) from the equalization filter 12 and converts the input signal q1(t) to an output signal q2(t) of defined slew rate.
The equalization control circuit 16 includes first and second scalars 22 and 24, an adder 26, and an integrator 28. The first and second scalars 22 and 24 respectively calculate the slew rates of the input and output signals q1(t) and q2(t) of the slicer 14. The adder 26 adds the output values of the first and the second scalars 22 and 24 and generates an error sum e(t). The integrator 28 integrates the sum e(t) and generates the gain control signal 20. With this structure, the equalization control circuit 16 calculates a slew rate error of the received signal r(t) by detecting the amplitude of the received signal and determines a gain adjustment amount (gain control signal 20) of the VGA 18 in accordance with the calculated slew rate error. Thus, the analog equalizer of FIG. 1 uses the slew rate error of the received signal r(t) as criteria for adaptive control (gain equalization control).
FIG. 2 is a waveform diagram showing an example of the operation of the analog equalizer of FIG. 1. When receiving serial data (“TX OUTPUT”) that is transmitted over the channel, the equalization control circuit 16 detects distortions in the rising and falling edges of the serial data to determine the gain adjustment amount of the equalization filter 12 to cancel such distortions.
Referring again to FIG. 1, the output signal q2(t) of the slicer 14 is provided via a differential amplifier 30 to an over sampler 32. The over sampler 32 over-samples the (serial data) output by the differential amplifier 30 under the frequency control of a phase lock loop (PLL) circuit 34. Here, “over-samples” refers to taking multiple samples of a received bit over the bit duration guided by multiple clock phases generated by the PLL circuit 34. A clock data recovery (CDR) circuit 36 determines the sign of the received serial data based on the over sampled bits output from the over sampler 32 and outputs the extracted data.
In this manner, a conventional analog adaptive channel equalizer includes not only the equalization filter 12 but also a large number of analog components such as the slicer 14 and the equalization control circuit 16. Thus, the conventional analog adaptive channel equalizer generally requires a long design time and large circuit areas. Further, the analog equalizer has poor design flexibility and reusability and is difficult to test. Thus, facilitated design, or so-called first-pass silicon, is relatively difficult to realize.
“A 6.4-Gb/s CMOS SerDes Core With Feed-Forward and Decision-Feedback Equalization”, in IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 40, No. 12, December 2005 describes an example of a digital equalizer. A typical digital equalizer such as a decision-feedback equalizer (DFE) calculates the channel-impulse response represented in the form of tap coefficients of the equalization filter. Further, the DFE generates a weighted sum of previous samples that can be used as a correction signal for canceling out ISI in the received sample. Here, weighted sum is based on the values of filter tap coefficients. The cancellation of the ISI is performed at the serial bit rate. Thus, a timing critical path may be produced if the DFE is applied to the receiver of a high-speed serial interface, particularly, at multi-Gbps bands. Normally, a separate custom circuit must be implemented to close the timing for such a critical path. Additionally, in an equalizer such as a DFE, the calculation of the weighted sum is computation intensive. This makes the overall channel equalization scheme more complex.
It would be advantageous to have a digital equalizer designed for flexibility, ease of implementation, and reusability, and which has a relatively small foot print.